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Two Hardware Engineering Req's open @ Cisco
Written by Suleman Shahid
Monday, 25 December 2006
There are two Signal Integrity/Hardware Engineering Req's open at Cisco Systems. Experienced candidates would be a plus and are prefered, however fresh college grads with relevant course work will be considered. If interested, email me your resume at
Thanks,
Abdulrahman Rafiq San Jose, Ca.
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DESCRIPTION: Join Cisco Systems, DSSTG ASIC Signal Integrity and Packaging Design Group for an exciting opportunity to share the responsibilities for the design, analysis and testing of high-speed ASICs and Packaging solutions. You will interface with ASIC and System Design teams as well as technology providers to solve complex design challenges.
BACKGROUND: You will contribute to the signaling and interconnect technology selection, definition and simulation of high-speed interconnects using simulation tools such HSPICE, HFSS, CST, Matlab, Sigrity Tools, ADS. The validation of all of the above using TDR, Network Analyzer, BERTs, Oscilloscopes and other lab equipment's. You will also play a key-role in the ASIC I/O Buffer structure definition and selection. Design rule generation of Package design, influence the design of packages, extract package models for SSN and Power Integrity Analysis. You will experience the challenge of a full end-to-end SerDes Channel simulation for our next generation ASICs. Understanding of SerDes Architecture is desired.
The ability to work well in a diverse environment and a solid understanding of electrical and physical aspects of high-speed digital design are key requirements. Expert knowledge of signal integrity fundamental theory and phenomena, transmission line theory, computational electromagnetic techniques (FEM, Mom, FDTD) in the time and frequency domains, jitter analysis and reduction are significant plusses.
You will assess timing, noise margin, crosstalk, signal loss and signal integrity of all clocks and critical data signaling and develop noise and timing budgets. Familiarity with high speed I/Os such as CML(SerDes), HSTL, SSTL, LVDS, LVPECL and memory technologies as QDR, DDR is a plus. Understanding the challenges required to solve source synchronous bus design is essential. Experience in High Speed ASIC design is a plus. Good documentation skills, communication/customer interaction skills also required.
BSEE or MSEE or PhD with related experience. Knowledge of UNIX, C, C++, Perl and scripting is desired.
